Integrated circuits comprise a body of a semiconductor material having formed therein various electrical components, such as transistors, diodes, capacitors, resistors, etc., which are connected together to form a desired circuit. Fabrication of an integrated circuit requires the use of many process techniques, such as depositions of various types, oxide growth, etching, ion-implantation, diffusion, heat treatment, etc. Each of these process techniques has its specific potential to cause crystalline defects in the semiconductor body. Specifically, for example, one of the process steps, formation of deep trenches, may generate dislocations. The contamination with metals during etching and cleaning has been correlated with stacking faults. Once the crystalline defects are formed, other processing techniques can increase the density of the crystalline defects to a level which adversely affects the operation of the integrated circuit. Whether a particular process of making an integrated circuit contains steps which create undesirable crystalline defects which adversely affect the electrical characteristics of the integrated circuit can only be determined after the integrated circuit is completely formed and can be electrically tested. For a complex fabrication process, this may take up to several weeks to several months. The interpretation of the results may be complicated because much of the data is not obviously evident to be directly related to crystalline defects, or directly correlated to any of the process steps. Spacial variations, like the temperature distribution across a wafer's surface, or wafer arrangement during processing, may come into play and hide why defects are formed. In a sequential type of development, after changes are made to the process, it takes a long time to fabricate another integrated circuit so as to determine whether the changes actually reduced or eliminated the undesirable crystalline defects.
Various attempts have been made during the development of a process for fabricating a particular integrated circuit to try to determine which steps of a long process may cause the creation of undesirable crystalline defects in the semiconductor body. One technique is to start out with a plurality of starting wafers. At various steps of the process a different wafer is removed and tested for possible defects. This technique has a disadvantage that it uses up a number of the wafers for testing during the process so that there are only a few wafers left at the end of the process for testing of completed integrated circuits. Also, there may be several steps which cause an undesirable effect so that pulling a wafer at a particular step of the process may not disclose which step actually caused the problem. For example, an etching step may cause some defects, but later heating steps may increase the defects to an undesirable level. The higher the process complexity, the lower the probability of combining test results of different wafers to make a determination as to what may have caused the creation of crystalline defects. Since there are a large number of chips on each wafer, if chip-to-chip variation is larger than wafer-to-wafer variation, it would be highly difficult to determine the problem(s) causing crystalline defects with the approach described above. Vertical tracking of monitor wafers has to assume a constant process and only approaches a solution by an educated guess after the analysis of various samples has been done. Thus, pulling and testing a wafer after an etching step does not necessarily result in a complete finding of a problem. Pulling a wafer after a heating step does not necessarily indicate where the problem initially occurred. Therefore, it is desirable to have a method for determining which step(s) of a process cause undesirable crystalline defects without using up a large number of wafers.
The dependence on various parameters cannot be correlated by a simple mono-causal analytical approach because the pulling of wafers after critical process steps and the investigation of failed cells typically does not provide enough information. In general, nucleation centers for the formation of dislocations are generated in damaged and highly stressed substrates or in contaminated wafers. Dislocations are often detected after low thermal budget annealing processes of high dose implantations into structure wafers with topography. Wafers that do not have any circuit features therein may not show any dislocations when subjected to the same high dose implants as wafers with circuit features therein. Crystal defect density is enhanced by the injection of impurities into a stressed substrate with a high point defect concentration. Crystal defects nucleate at sites of high stress. One such site can be the bottom of a box isolation (shallow trench) at high compressive stress caused by different oxidation rates on different crystal planes which may act as a Frank-Read source. This in turn results in punching out glide dislocations into the depletion zone which increases the junction leakage. The annealing processes provide means of enhancing the formation of dislocation as well as removing crystal damage depending on the actual process flow. Thus, contributing factors for formation of crystalline defects may be quite separated in an integrated process. Annealing steps and their sequence (high temperature/low temperature) are especially subject to the formation of dislocations.